Clock frequency is not configurable. The min clock frequency is 80kHz. Max permissible clock frequency is not specified in master, but this is done by bus establishment.
During bus establishment:
- the min BISS timeout of the slaves is determined and configured
- the min and max permissible MA clock pulse is deternmined (depends on master, slaves and topology)
- CRC start values are configured in master and slaves
- processing time parameter is configured in the master
- the min cycle time duration is determined (based on bits in data area, processing time, MA clock rate and configured BISS timeout)
During bus establishment:
- the min BISS timeout of the slaves is determined and configured
- the min and max permissible MA clock pulse is deternmined (depends on master, slaves and topology)
- CRC start values are configured in master and slaves
- processing time parameter is configured in the master
- the min cycle time duration is determined (based on bits in data area, processing time, MA clock rate and configured BISS timeout)
發佈於:施耐德電機Taiwan
